DocumentCode :
1847328
Title :
Latency exploitation in circuit simulation by sparse matrix techniques
Author :
van Eijndhoven, J.T.J. ; van Stiphout, M.T.
Author_Institution :
Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
fYear :
1988
fDate :
7-9 June 1988
Firstpage :
623
Abstract :
The most important operations for a circuit simulator are component model linearization, updating the network matrix, performing large unsymmetric decomposition on this matrix, and solving the network variables by forward and backward substitution. Methods are presented to keep all these operations localized to the part of the network that is active at the current time point, thus obtaining a considerable reduction in computational effort. The methods depend upon the sparse matrix structure itself, yielding a very effective fine-grained latency use, contrary to methods based on the large blocks specified by the circuit hierarchy. Results obtained from an implementation of the algorithms in a piecewise linear circuit simulator with an implicit multirate integration scheme are presented.<>
Keywords :
circuit analysis computing; integration; matrix algebra; piecewise-linear techniques; algorithms; circuit simulation; component model linearization; fine-grained latency use; large unsymmetric decomposition; multirate integration scheme; network matrix update; piecewise linear circuit simulator; sparse matrix techniques; Circuit simulation; Computational modeling; Computer networks; Delay; Intelligent networks; Jacobian matrices; Matrix decomposition; Piecewise linear techniques; Sparse matrices; Transient analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo, Finland
Type :
conf
DOI :
10.1109/ISCAS.1988.15003
Filename :
15003
Link To Document :
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