Advanced Encryption Standard (AES) implementation with increased DPA resistance and low overhead

The use of the Advanced Encryption Standard (AES) has become pervasive in a large number of communication applications. The hardware to implement AES is non trivial and as a result it has a significant overhead in its raw form. Despite the algorithm being inherently secure, side channel attacks have exposed potential weaknesses via the implementation route, particularly power analysis. As a result, much effort has been expended in identifying techniques to mask the power signature that can give away the secret key. Unfortunately, the hardware overhead is usually a significant proportion of the size of the original algorithm and in addition, the key can sometimes still be ascertained due to manufacturing differences (such as track lengths) still delivering aspects of the key in a power signature. This paper describes an approach that requires a simple modification to the implementation of the AES algorithm, without altering its basic characteristics, which provides a significantly improved strength against side channel attacks with a minimal additional hardware overhead.