DocumentCode
1847470
Title
Implementation of AES S-Boxes using combinational logic
Author
Rachh, Rashmi Ramesh ; Mohan, P. V Ananda
Author_Institution
Dept. of Comput. Sci., KLE Coll. of Eng. & Technol., Belgaum
fYear
2008
fDate
18-21 May 2008
Firstpage
3294
Lastpage
3297
Abstract
In this paper, two approaches for implementation of the 8-bit S-Box suitable for FPGA based solutions are considered. These use (a) synthesis of the logic functions using Boolean simplification of the truth table of all the columns and (b) synthesis of the ANF (Algebraic Normal form) logic functions using AND and EXOR gates. The hardware and computation time evaluation for both the options are also presented.
Keywords
Boolean algebra; field programmable gate arrays; logic design; AES 8-bit S-boxes; ANF; Boolean simplification; FPGA; algebraic normal form; combinational logic; field programmable gate array; truth table; Costs; Cryptography; Delay; Field programmable gate arrays; Hardware; Iterative algorithms; Logic functions; NIST; Read only memory; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location
Seattle, WA
Print_ISBN
978-1-4244-1683-7
Electronic_ISBN
978-1-4244-1684-4
Type
conf
DOI
10.1109/ISCAS.2008.4542162
Filename
4542162
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