A full-custom design of AES SubByte module with signal independent power consumption

Author

Li, Liang ; Han, Jun ; Zeng, Xiaoyang ; Zhao, Jia

Author_Institution

State-Key Lab. of ASIC & Syst., Fudan Univ., Shanghai

fYear

2008

fDate

18-21 May 2008

Firstpage

3302

Lastpage

3305

Abstract

A full-custom design of AES SubByte module based on sense amplifier based logic is proposed in this paper. Power consumption of this design is independent of both value and sequence of data. Therefore this design is resistant to power analysis attack. This design is implemented using SMIC 0.18 um CMOS technology. Simulation results show that it can work at the frequency of 83.3 MHz, and its total area is about 0.85 mm². This design is suitable for application in the hardware implementation of symmetric-key cryptographic devices that have high security demand.

Keywords

CMOS integrated circuits; integrated circuit design; logic circuits; power consumption; AES SubByte module; CMOS technology; full-custom design; power analysis; sense amplifier based logic; signal independent power consumption; symmetric-key cryptographic devices; CMOS logic circuits; Capacitance; Cryptography; Energy consumption; Frequency; Information security; Logic design; Pipelines; Power amplifiers; Signal design;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Conference_Location

Seattle, WA

Print_ISBN

978-1-4244-1683-7

Electronic_ISBN

978-1-4244-1684-4

Type

conf

DOI

10.1109/ISCAS.2008.4542164

Filename

4542164