DocumentCode
1847524
Title
Design of a 18 GHZ divide-by-4 prescaler using 1µM GaAs HBT technology
Author
Li, Chengzhi ; Qu, Xiaofeng ; Lu, Kejie ; Sui, Wenquan
Author_Institution
Zhejiang California Int. NanoSystems Inst., Zhejiang Univ., Hangzhou, China
fYear
2009
fDate
15-17 Dec. 2009
Firstpage
354
Lastpage
357
Abstract
This paper describes the design of a 18 GHz high frequency divide-by-4 prescaler using WIN Foundry 1 μm GaAs HBT technology. The prescaler was designed with differential operation on the base of two master-slave D-latches with the input signal on the clock terminals of the latches. Parasitic effects of the circuit layout, which would reduce the prescaler´s maximum working frequency, are taken into considerations during the post co-simulation of the circuit layout at high frequency range. Modifications to the layout, based on the EM simulation results, are made to restore the designed the high frequency performance. The designed prescaler operates at 5.0 V supply, consumes about 400 mW power and its phase noise is -151.67 dBm at 100 KHz. The divide-by-4 prescaler is suitable for RF and microwave applications between S and Ku bands.
Keywords
III-V semiconductors; circuit layout; frequency dividers; gallium arsenide; heterojunction bipolar transistors; phase noise; GaAs; HBT technology; RF applications; WIN Foundry 1; circuit layout; clock terminals; divide-by-4 PRESC ALER; frequency 18 GHz; master-slave D-latches; microwave applications; parasitic effects; size 1 μm; Circuit simulation; Clocks; Foundries; Frequency conversion; Gallium arsenide; Heterojunction bipolar transistors; Latches; Master-slave; Phase noise; Signal design; GaAs; HBT; co-simulation; current mode logic; high frequency prescaler; static frequency divider;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications (MICC), 2009 IEEE 9th Malaysia International Conference on
Conference_Location
Kuala Lumpur
Print_ISBN
978-1-4244-5531-7
Type
conf
DOI
10.1109/MICC.2009.5431529
Filename
5431529
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