Switching activity reduction in low power Booth multiplier

A new low power multiplication algorithm for reducing the switching activity through operand decomposition for Radix-8 Booth multiplier is proposed. The proposed algorithm incorporates our proposed Redundant Binary Signed Digit (RBSD) Modified Booth-3 (Radix-8) encoding scheme to generate RBSD partial product rows and low power RB Adder unit designed for accumulation and thereby circumventing the need to generate hard multiples and sign extension. Experimental results show a reduction of 21% in dynamic power consumption and at least 44% reduction in Energy Delay Product (EDP) with a penalty of 4% in area.