A dynamic address decode circuit for implementing range addressable look-up tables

A Range Addressable Look Up Table (RALUT) is a non-linear memory storage element that has been shown to significantly reduce hardware requirements for matching data in particular applications. However, its ability to perform parallel pattern matching on large words can be applied in many areas. Most of the RALUT circuits presented in literature thus far are built with logic gates and tri-state buffers so that they are easily synthesizable and implemented with other components of the overall design. These circuits are not competitive with modern memory in terms of area, timing, power and functionality. The only significant difference between a RALUT and a standard LUT is the address decoding system. In this paper, we will show a preliminary dynamic address decode circuit which can be used to build a scalable full custom read-only RALUT implementations. We will show significant reductions in area, timing and power compared to a previously published synthesized version.