A power-aware 2-dimensional bypassing multiplier using cell-based design flow

This paper presents a low power digital multiplier design by taking advantage of a 2-dimensional bypassing method in cell-based design flow. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally partial product or the vertically operand is zero. Thorough cell-based design flow post-layout simulations show that the power delay product of the proposed 8times8 multiplier design is reduced by more than 13.8% compared to prior designs.