A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop

A 333 MHz-1 GHz all-digital multiphase delay-locked loop with precise multi-phase output has been designed with TSMC 130 nm CMOS technology model. A modified binary search algorithm is proposed to match up a linear approximate delay element (LADE). The LADE property of linearity and insensitive to PVT variations is good for digitally-controlled delay element. The lock-in time could be reduced down to 14 reference clock cycles, and enhance the operation range based on LADE/binary search algorithm co-operate effort. The timing error caused by process mismatch is further reduced by proposed rapid self-calibration (RSC) algorithm. A calibration unit is designed based on RSC algorithm, which reduces the maximum timing error to less than 9 ps when DLL is operating at 500 MHz. The entire calibration unit could be turned off after calibration procedure is complete to reduce power consumption. The total power dissipation of the all-digital self-calibrated multiphase delay-locked loop is 5.2 mW at 1 GHz with a 1.2 V power supply.