A general model for differential power analysis attacks to static logic circuits

In this paper, a general model of multi-bit differential power analysis (DPA) attacks to static logic circuits is proposed, with emphasis on symmetric-key cryptographic algorithms. The main parameters that are of interest in practical DPA attacks are analytically derived by introducing suitable approximations. Several interesting properties of DPA attacks are derived, allowing a deep understanding of the vulnerability of algorithms and circuits. The proposed model was validated by means of experimental measurements on an FPGA implementation of the Advanced Encryption Standard (AES) algorithm. The model accuracy is shown to be adequate, as the resulting error is always lower than 11%.