• DocumentCode
    1847876
  • Title

    A variant of a radix-10 combinational multiplier

  • Author

    Dadda, Luigi ; Nannarelli, Alberto

  • Author_Institution
    Politec. di Milano, Milano, Univ. della Svizzera italiana, Milan
  • fYear
    2008
  • fDate
    18-21 May 2008
  • Firstpage
    3370
  • Lastpage
    3373
  • Abstract
    We consider the problem of adding the partial products in the combinational decimal multiplier presented by Lang and Nannarelli. In the original paper this addition is done with a tree of decimal carry-save adders. In this paper, we treat the problem using the multi-operand decimal addition previously published by Dadda, where the sum of each column of the partial product array is obtained first in binary form and then converted to decimal. The multiplication, using a 90 nm CMOS technology, in this modified scheme takes 2.51 ns, while in the original scheme it takes 2.65 ns. The area of the two schemes is roughly the same.
  • Keywords
    CMOS logic circuits; adders; combinational circuits; digital arithmetic; multiplying circuits; CMOS technology; binary form; combinational decimal multiplier; decimal carry-save adders; multi-operand decimal addition; partial product array; radix-10 combinational multiplier; size 90 nm; time 2.51 ns; time 2.65 ns; CMOS technology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
  • Conference_Location
    Seattle, WA
  • Print_ISBN
    978-1-4244-1683-7
  • Electronic_ISBN
    978-1-4244-1684-4
  • Type

    conf

  • DOI
    10.1109/ISCAS.2008.4542181
  • Filename
    4542181