Optimization technique for flip-flop inserted global interconnect

The design targets of an interconnect are to ensure less delay cycles, high reliability and low power consumption at the same time. This paper presents an in-depth analysis of the dependencies of the reliability (in terms of bit error rate (BER)) and the power consumption of wire pipelining scheme on the number of inserted flip-flops and the size of repeaters. To trade off the design targets, a methodology is developed to optimize the repeater size and the number of flip-flops inserted, which maximizes a user-specified figure of merit. This methodology is demonstrated by calculating the optimal solutions for interconnect pipelining for some International Technology Roadmap for Semiconductor technology nodes.