Title :
Design optimization of One-Turn Helix - a novel compliant off-chip interconnect
Author :
Zhu, Qi ; Ma, Lunyu ; Sitaraman, Suresh K.
Author_Institution :
Comput.-Aided Simulation of Packaging Reliability Lab., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. One-Turn Helix (OTH), is designed as a compliant off-chip interconnect that allowing wafer-level probing and packaging without underfill. It has excellent compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of OTH is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, we study the effect of geometry parameters on mechanical and electrical performance of OTH. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH. Response surface methodology and an optimization technique have been used to select the optimal OTH structure parameters.
Keywords :
integrated circuit design; integrated circuit interconnections; integrated circuit packaging; surface fitting; thermal expansion; IC fabrication; One-Turn Helix; Si; coefficient of thermal expansion mismatch; compliant off-chip interconnect; design optimization; electrical characteristics; electronic packaging; mechanical compliance; organic substrate; response surface methodology; silicon die; wafer-level packaging; wafer-level probing; Costs; Design optimization; Electronic packaging thermal management; Electronics packaging; Fabrication; Geometry; Integrated circuit packaging; Silicon; Thermal expansion; Wafer scale integration;
Conference_Titel :
Thermal and Thermomechanical Phenomena in Electronic Systems, 2002. ITHERM 2002. The Eighth Intersociety Conference on
Print_ISBN :
0-7803-7152-6
DOI :
10.1109/ITHERM.2002.1012541