DocumentCode :
1848215
Title :
Advanced circuit technology to realize post giga-bit DRAM
Author :
Okuda, Takashi
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Kanagawa, Japan
fYear :
1998
fDate :
27-29 May 1998
Firstpage :
2
Lastpage :
5
Abstract :
A 4-Gb DRAM with multilevel-storage memory cells has been developed. This large memory capacity is achieved by storing data at four levels, each level corresponding to the two-bit-data storage of a single memory cell. The four-level storage reduces the effective cell size by 50%. A sense amplifier that uses charge coupling and charge sharing was developed for the four level sensing and restoring operations. A 4-Gb DRAM was fabricated using 0.15-μm CMOS technology, that measures 986 mm2 in area. The area of the memory cell is 0.23 μm2. Its capacitance of 60 fF is achieved by use of a high-dielectric-constant material (Ba,Sr)TiO3
Keywords :
DRAM chips; memory architecture; (BaSr)TiO3; 0.15 mum; 4 Gbit; 60 fF; CMOS technology; DRAM; memory capacity; multilevel-storage memory; two-bit-data storage; Circuits; Random access memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multiple-Valued Logic, 1998. Proceedings. 1998 28th IEEE International Symposium on
Conference_Location :
Fukuoka
ISSN :
0195-623X
Print_ISBN :
0-8186-8371-6
Type :
conf
DOI :
10.1109/ISMVL.1998.679266
Filename :
679266
Link To Document :
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