A reconfigurable MAC architecture implemented with mixed-Vt standard cell library

In this paper, a 32-bit reconfigurable multiplication- accumulation architecture, which can execute flexibly one 32times32, two 16times16 or four 8times8 two´s complement multiply- accumulation, is proposed and demonstrated. It is based on the modified Booth encoding scheme and designed with techniques of reducing sign-extension bits, removing one extra partial product row and adjusting the positions of hot signals but with elegant modifications. It is implemented with a 130nm mixed-Vt CMOS standard cell library and shows saving of area and power consumption by approximately 16% and 14% respectively as compared to the previous design.