Title :
Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)
Abstract :
The following topics are dealt with: Web and IP based design; embedded processor design; passive model order reduction; post-CMOS technology; formal verification; high level specification and design; timing abstraction; E-textiles; analog intellectual property; low-power system design; fabric-driven logic synthesis; memory management and address optimization in embedded systems; optics in EDA; nanometer design; DFT, BIST and diagnosis techniques; embedded system design; equivalence verification; embedded software automation; reconfigurable computing; test methods for non-classical faults; 10M gate ASIC design; power distribution; analog synthesis and design methodology; low-power physical design; unified tools for SoC embedded systems; multi-voltage, multi-threshold design; simulation techniques; design methodologies for network applications; analog modeling; routing and buffering; system on chip design; timing analysis and memory optimization; processors and accelerators; EDA drivers; cross-talk noise analysis and management; SoC test cost reduction; scheduling techniques for embedded systems; SoC design for yield improvement; Boolean satisfiability; inductance and substrate analysis; processors and communication networks; energy efficient mobile computing; floorplanning and placement; circuit effects in static timing; design space exploration for embedded systems; behavioral synthesis.
Keywords :
analogue integrated circuits; application specific integrated circuits; buffer circuits; built-in self test; circuit CAD; circuit layout CAD; design for testability; embedded systems; high level synthesis; industrial property; integrated circuit design; integrated circuit testing; integrated circuit yield; integrated optoelectronics; network routing; telecommunication equipment; ASIC design; BIST; Boolean satisfiability; DFT; E-textiles; IP based design; SoC design for yield; SoC embedded systems; SoC test cost reduction; Web based design; address optimization; analog intellectual property; analog synthesis; behavioral synthesis; buffering; component placement; design automation; embedded processor design; embedded software automation; embedded system design; energy efficient mobile computing; fabric-driven logic synthesis; floorplanning; formal verification; high level design; high level specification; inductance; low-power system design; memory management; memory optimization; multi-voltage multi-threshold design; nanometer design; nonclassical fault tests; optics based EDA; passive model order reduction; physical design; post-CMOS technology; power distribution; reconfigurable computing; routing; scheduling techniques; simulation; substrate analysis; telecommunications network applications; timing abstraction; timing analysis;
Conference_Titel :
Design Automation Conference, 2002. Proceedings. 39th
Conference_Location :
New Orleans, LA, USA
Print_ISBN :
1-58113-461-4
DOI :
10.1109/DAC.2002.1012583