DocumentCode
1849216
Title
A fast on-chip profiler memory
Author
Lysecky, Roman ; Cotterell, Susan ; Vahid, Frank
Author_Institution
Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA
fYear
2002
fDate
2002
Firstpage
28
Lastpage
33
Abstract
Profiling an application executing on a microprocessor is part of the solution to numerous software and hardware optimization and design automation problems. Most current profiling techniques suffer from runtime overhead, inaccuracy, or slowness, and the traditional non-intrusive method of using a logic analyzer doesn´t work for today´s system-on-a-chip having embedded cores. We introduce a novel on-chip memory architecture that overcomes these limitations. The architecture, which we call ProMem, is based on a pipelined binary tree structure. It achieves single-cycle throughput, so it can keep up with today´s fastest pipelined processors. It can also be laid out efficiently and scales very well, becoming more efficient the larger it gets. The memory can be used in a wide-variety of common profiling situations, such as instruction profiling, value profiling, and network traffic profiling, which in turn can be used to guide numerous design automation tasks.
Keywords
circuit CAD; embedded systems; instruction sets; microprocessor chips; pipeline processing; system-on-chip; ProMem; common profiling situations; design automation problems; design automation tasks; embedded cores; instruction profiling; microprocessor; network traffic profiling; on-chip profiler memory; pipelined binary tree structure; runtime overhead; single-cycle throughput; system-on-a-chip; value profiling; Application software; Computer architecture; Design automation; Design optimization; Hardware; Logic; Memory architecture; Microprocessors; Runtime; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2002. Proceedings. 39th
ISSN
0738-100X
Print_ISBN
1-58113-461-4
Type
conf
DOI
10.1109/DAC.2002.1012589
Filename
1012589
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