An Algorithm Based on AVS Encoding on FPGA Multi-Core Pipeline

In view of the problem that the AVS encoding architecture on multi-cores have a high level of the intricacy, according to the data dependency of the encoding modules, combining with the advantages of the multi-core system in FPGA, a parallel algorithm based on GOP is proposed. This article built a single-core system based on XILINX FPGA first, then transplanted the AVS reference code RM5.2 to this system, and achieved the data of this single core system. After that, this article built a three-core system on that single-core system and achieved the algorithm based on GOP on the embedded system structure. The experimental results show that the parallel algorithm can effectively improve the speedup and the image quality is almost the same.