Title :
Congestion-driven codesign of power and signal networks
Author :
Su, Haihua ; Hu, Jiang ; Sapatnekar, Sachin S. ; Nassif, Sani R.
Author_Institution :
IBM Corp., Austin, TX, USA
Abstract :
Presents a global wire design methodology that simultaneously considers the performance needs for both signal lines and power grids under congestion considerations. An iterative procedure is employed in which the global routing is performed according to a congestion map that includes the resource utilization of the power grid, followed by a step in which the power grid is adjusted to relax the congestion in crowded regions. This adjustment is in the form of wire removal in noncritical regions, followed by a wire sizing step that overcomes the effects of wire removal. Experimental results show that the overall routability can be significantly improved while the power grid noise is maintained within the voltage droop constraint.
Keywords :
VLSI; circuit layout CAD; integrated circuit interconnections; integrated circuit layout; integrated circuit noise; iterative methods; network routing; wiring; congestion map; congestion-driven codesign; global routing; interconnect; iterative procedure; overall routability; power grid; power grid noise; power networks; resource utilization; signal networks; signal routing; voltage droop constraint; wire removal; wire sizing step; Algorithm design and analysis; Design methodology; Maintenance; Permission; Power grids; Resource management; Routing; Signal design; Voltage; Wire;
Conference_Titel :
Design Automation Conference, 2002. Proceedings. 39th
Print_ISBN :
1-58113-461-4
DOI :
10.1109/DAC.2002.1012595
