A High Efficient Pipelined Architecture for De-Blocking Filter in AVS

A high efficient pipelined architecture for the de-blocking filter in AVS is presented. The de-blocking filter stands in the fourth level in our video decoding pipeline. It filters the reconstructed pixels and sends filtered macro-block (MB) to the Reference Store. We use the novel pipeline architecture to realize real-time AVS HD video decoding under smaller chip area size. The simulation results show that our de-blocking can easily support real-time de-blocking of 1080p (1920×1080)@30fps video. The synthesized logic gate count is only 22.6 K (not including SRAM) when the maximum frequency is 148.5MHz under 0.18μm technology. It is valuable for platform-based design of AVS HD codec.