DocumentCode
1849738
Title
Automated timing model generation
Author
Daga, Ajay J. ; Mize, Loa ; Sripada, Subramanyam ; Wolff, Chris ; Wu, Qiuyang
Author_Institution
Synopsys, Inc., Hillsboro, OR, USA
fYear
2002
fDate
2002
Firstpage
146
Lastpage
151
Abstract
The automated generation of timing models from gate-level netlists facilitates IP reuse and dramatically improves chip-level STA runtime in a hierarchical design flow. In this paper we discuss two different approaches to model generation, the design flows they lend themselves to and results from the application of these model generation solutions to large customer designs.
Keywords
circuit CAD; industrial property; integrated circuit design; integrated circuit modelling; system-on-chip; timing; IP reuse; automated timing model generation; chip-level STA runtime; gate-level netlist; hierarchical design flow; system-on-a-chip; Algorithm design and analysis; Application software; Electronic design automation and methodology; Intellectual property; Libraries; Performance analysis; Permission; Runtime; System-on-a-chip; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2002. Proceedings. 39th
ISSN
0738-100X
Print_ISBN
1-58113-461-4
Type
conf
DOI
10.1109/DAC.2002.1012610
Filename
1012610
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