DocumentCode
1850416
Title
Transformation based communication and clock domain refinement for system design
Author
Sander, Ingo ; Jantsch, Axel
Author_Institution
R. Inst. of Technol., Stockholm, Sweden
fYear
2002
fDate
2002
Firstpage
281
Lastpage
286
Abstract
The ForSyDe methodology has been developed for system level design. In this paper we present formal transformation methods for the refinement of an abstract and formal system model into an implementation model. The methodology defines two classes of design transformations: (1) semantic-preserving transformations and (2) design decisions. In particular we present and illustrate communication and clock domain refinement by way of a digital equalizer system.
Keywords
circuit CAD; clocks; equalisers; formal verification; integrated circuit design; system-on-chip; ForSyDe methodology; SoC; clock domain refinement; design transformations; digital equalizer system; formal system model; formal transformation methods; implementation model; semantic-preserving transformations; system level design; transformation based communication; Clocks; Computational modeling; Design automation; Design engineering; Design methodology; Equalizers; Hardware; Integrated circuit modeling; Permission; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2002. Proceedings. 39th
ISSN
0738-100X
Print_ISBN
1-58113-461-4
Type
conf
DOI
10.1109/DAC.2002.1012636
Filename
1012636
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