A New Empirical Gate Capacitance Model for PHEMT and MESFET Transistors

This work deals with a nonlinear model for the gate-source capacitance CGS (VGS, VDS) and gate-drain capacitance CGD (VGS, VDS) of GaAs MESFET, HEMT and PHEMT transistors. An analytical bias dependent expression for modeling the CGS (VGS, VDS) and CGD (VGS, VDS) capacitances is developed. The CGS (VGS, VDS) and CGD (VGS, VDS) experimental values are obtained using a multibias extraction of the small signal equivalent circuit procedure. Good agreement between modeled and experimental data, as a function of gate-source and drain-source bias, is obtained. The main feature of the proposed nonlinear model is that no optimization is needed to achieve a good fit of modeled to experimental data.