A practical and efficient method for compare-point matching

Author

Anastasakis, Demos ; Damiano, Robert ; Ma, Hi-Keung Tony ; Stanion, Ted

fYear

2002

fDate

2002

Firstpage

305

Lastpage

310

Abstract

An important step in using combinational equivalence checkers to verify sequential designs is identifying and matching corresponding compare-points in the two sequential designs to be verified. Both non-function and function-based matching methods are usually employed in commercial verification tools. In this paper, we describe an heuristic algorithm using ATPG for matching compare-points based on the functionality of the combinational blocks in the sequential designs. Results on industrial-sized circuits show the methods are both practical and efficient.

Keywords

automatic test pattern generation; combinational switching; formal verification; logic partitioning; logic testing; sequential circuits; ATPG; combinational block functionality; combinational equivalence checkers; compare-point matching; function-based matching methods; heuristic algorithm; industrial-sized circuits; latch mapping; nonfunction-based matching methods; sequential design verification; vector generation partitioning; Algorithm design and analysis; Automatic test pattern generation; Circuits; Design methodology; Heuristic algorithms; Latches; Logic design; Permission; Production; Signal design;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2002. Proceedings. 39th

ISSN

0738-100X

Print_ISBN

1-58113-461-4

Type

conf

DOI

10.1109/DAC.2002.1012640

Filename

1012640