Title :
Signal integrity fault analysis using reduced-order modeling
Author :
Attarha, Amir ; Nourani, Mehrdad
Author_Institution :
Center for Integrated Circuits & Syst., Texas Univ., Richardson, TX, USA
Abstract :
This paper aims at analysis of signal integrity for the purpose of testing high speed interconnects. This requires taking into account the effect of inputs as well as parasitic RLC elements of the interconnect. To improve the analysis/simulation time in integrity fault testing, we use reduced-order modeling that essentially performs the analysis in the frequency domain. To demonstrate the generality and usefulness of our method, we also discuss its application for test pattern generation targeting signal integrity loss.
Keywords :
RLC circuits; automatic test pattern generation; distributed parameter networks; fault simulation; frequency-domain analysis; integrated circuit interconnections; integrated circuit modelling; integrated circuit testing; reduced order systems; frequency domain analysis; high speed interconnect testing; integrity fault testing; interconnect inputs; parasitic RLC elements; reduced-order modeling; signal integrity fault analysis; signal integrity loss; test pattern generation; Circuit faults; Circuit testing; Delay; Frequency domain analysis; Integrated circuit interconnections; Integrated circuit modeling; Performance analysis; Reduced order systems; Signal analysis; Test pattern generators;
Conference_Titel :
Design Automation Conference, 2002. Proceedings. 39th
Print_ISBN :
1-58113-461-4
DOI :
10.1109/DAC.2002.1012651
