C-17A mission computer internal built-in test and I-level fault logging

This paper describes the C-17A mission computer (MC) internal built-in test (BIT) and intermediate level (I-Level) fault logging strategies. The MC is the primary component of the C-17A mission computer/electronic display subsystem (MC/EDS). The MC/EDS is intended to provide flight management functions for the C-17A aircraft in addition to display processing and display of mission, flight, engine, aircraft status and other related information to the flight crew. The MC is designed to be a highly reliable and fail-safe computer to prevent inadvertent display of hazardously misleading information on the head-up and head-down displays. The MC subsystem uses triple modular redundancy and voting schemes to detect the failures and isolate them to a line replaceable unit (LRU). The fault detection circuits in the MC detect the faults concurrently with the normal operation and report them to the MC CPU. The self-test programs are comprised of separately executing software/firmware modules. These modules when combined with the BIT hardware achieve a high degree of fault detection coverage. In this paper we present the MC internal BIT modes such as power-up, periodic, and initiated BIT. The software BIT mechanisms are discussed and the MC I-level fault logging approach is reviewed