A dynamically controlled and refreshed low-power level-up shifter

Author

Huang, Zhengrong ; Savaria, Yvon ; Sawan, Mohamad

Author_Institution

Groupe de Recherche en Microelectron., Ecole Polytech. de Montreal, Que., Canada

Volume

1

fYear

2004

fDate

25-28 July 2004

Abstract

A low-power level-up shifter circuit is presented. This circuit produces a digital output signal in the 0-300 V range from a digital input signal in the 0-5 V range. The proposed circuit reduces power consumption through two key features: dynamic charge control that decreases the power dissipated in the level-up stage, and a "break before make" logic that reduces the short-circuit power of the output stage. An asynchronous control circuit is designed to refresh the dynamic node so that the proposed circuit can work at any low frequency. Detailed design methodologies are described in this paper. This circuit is designed and implemented under DALSA semiconductor\´s 0.8 μm 5 V/HV CMOS/DMOS technology. Simulation results validate its operation and performance.

Keywords

CMOS digital integrated circuits; asynchronous circuits; integrated circuit design; logic design; low-power electronics; power integrated circuits; semiconductor technology; voltage multipliers; 0 to 300 V; 0.8 micron; DALSA semiconductor CMOS technology; DALSA semiconductor DMOS technology; asynchronous control circuit design; break before make logic; digital input signal; digital output signal; dynamic charge control; low power level-up shifter circuits; power consumption; short circuit power; CMOS technology; Driver circuits; Energy consumption; Flat panel displays; Frequency; Logic circuits; Logic devices; Plasma displays; Vehicle dynamics; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on

Print_ISBN

0-7803-8346-X

Type

conf

DOI

10.1109/MWSCAS.2004.1353906

Filename

1353906