DocumentCode
1851503
Title
A switched-voltage high-accuracy sample/hold circuit
Author
Matsumot, Hiroki ; Murao, Kenji ; Ohno, Kenji
Author_Institution
Fac. of Eng., Miyazaki Univ., Japan
Volume
1
fYear
2004
fDate
25-28 July 2004
Abstract
In this paper, three switched-voltage (SV) sample/hold (S/H) circuits are presented to compensate for clock-feed-through (CFT) and channel-length modulation effect. They consist of a CMOS SV-delay cell. Thus, the configuration is very simple. The proposed circuits can be operated using simple nonoverlapping two phase clocks. The performance is verified by simulations on PSpice.
Keywords
CMOS integrated circuits; SPICE; circuit simulation; sample and hold circuits; CMOS switched voltage-delay cell; PSpice simulation; channel length modulation effect; clock feed through effect; switched voltage sample-hold circuits; CMOS technology; Clocks; Delay; Equations; MOS devices; MOSFETs; Switches; Switching circuits; Variable structure systems; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on
Print_ISBN
0-7803-8346-X
Type
conf
DOI
10.1109/MWSCAS.2004.1353908
Filename
1353908
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