DocumentCode
1851683
Title
Regularization of hierarchical VHDL-AMS models using bipartite graphs
Author
Mades, Jochen ; Glesner, Manfred
Author_Institution
Infineon Technol. AG, Munich, Germany
fYear
2002
fDate
2002
Firstpage
548
Lastpage
551
Abstract
The powerful capability of VHDL-AMS to describe complex continuous systems in form of differential algebraic equations (DAEs) often leads to problems during numerical simulation. This paper presents a discrete algorithm to analyze unsolvable DAE systems and to correct the underlying hierarchical VHDL-AMS description automatically in interaction with the designer, avoiding time-consuming manual error correction.
Keywords
VLSI; circuit simulation; differential equations; graph theory; hardware description languages; integrated circuit design; mixed analogue-digital integrated circuits; analog design; bipartite graphs; complex continuous systems; differential algebraic equations; discrete algorithm; hierarchical VHDL-AMS models; numerical simulation; regularization; unsolvable DAE systems; Algorithm design and analysis; Bipartite graph; Differential algebraic equations; Differential equations; Error correction; Mathematics; Numerical simulation; Packaging; Permission; Power system modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2002. Proceedings. 39th
ISSN
0738-100X
Print_ISBN
1-58113-461-4
Type
conf
DOI
10.1109/DAC.2002.1012685
Filename
1012685
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