A precision CMOS sample-and-hold circuit with low temperature drift for integrated transducers

Author

Chan, P.K. ; Cui, J.

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore

Volume

1

fYear

2004

fDate

25-28 July 2004

Abstract

A new precision CMOS sample-and-hold (S/H) circuit for integrated transducers is proposed. The circuit utilizes auto-zero technique for circuit error sampling, parallel bootstrap switch for reducing switch sampling error due to dominant switch charge injection and chopper-stabilized differential difference amplifier for accurate canceling common-mode error components. Not only does the S/H circuit exhibit low temperature drift, it eliminates 1/f noise and dc offset of op-amp and MOS switch errors. The HSPICE simulations have validated the results using AMS 0.6 μm CMOS process parameters in a single 5 V supply.

Keywords

1/f noise; CMOS analogue integrated circuits; bootstrap circuits; choppers (circuits); circuit simulation; differential amplifiers; integrated circuit design; operational amplifiers; sample and hold circuits; sampling methods; transducers; 0.6 micron; 1/f noise elimination; 5 V; CMOS sample and hold circuit; HSPICE simulation; MOS switch error elimination; auto-zero technique; chopper stabilized differential difference amplifier; circuit error sampling; common mode error components; integrated transducers; low temperature drift; op-amp error elimination; parallel bootstrap switch; switch charge injection; switch sampling error reduction; Circuit noise; Circuit simulation; Differential amplifiers; Noise cancellation; Operational amplifiers; Sampling methods; Switches; Switching circuits; Temperature; Transducers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on

Print_ISBN

0-7803-8346-X

Type

conf

DOI

10.1109/MWSCAS.2004.1353918

Filename

1353918