A precision CMOS sample-and-hold circuit with low temperature drift for integrated transducers

A new precision CMOS sample-and-hold (S/H) circuit for integrated transducers is proposed. The circuit utilizes auto-zero technique for circuit error sampling, parallel bootstrap switch for reducing switch sampling error due to dominant switch charge injection and chopper-stabilized differential difference amplifier for accurate canceling common-mode error components. Not only does the S/H circuit exhibit low temperature drift, it eliminates 1/f noise and dc offset of op-amp and MOS switch errors. The HSPICE simulations have validated the results using AMS 0.6 μm CMOS process parameters in a single 5 V supply.