Design techniques for CMOS very-low-voltage operational amplifiers with enhanced power supply rejection ratio

Author

Lee, Tsung-Sum ; Liu, Wei-Chang ; Chun-Teng Chung

Author_Institution

Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan

Volume

1

fYear

2004

fDate

25-28 July 2004

Abstract

Two very-low-voltage operational amplifiers in standard 0.35 μm CMOS process are presented. They have adopted folded-mirror active load and folded-cascode active load, respectively in the input stage, which save input swing. Cascode compensation offers a much improved high-frequency PSRR. Simulation results are provided and the corresponding performances are discussed and compared. Simulation results indicate that those circuits show superior power supply rejection at high frequencies.

Keywords

CMOS analogue integrated circuits; circuit simulation; integrated circuit design; low-power electronics; operational amplifiers; 0.35 micron; CMOS operational amplifiers; circuit simulation; enhanced power supply rejection ratio; folded cascode active load; folded mirror active load; integrated circuit design; very low voltage operational amplifiers; CMOS process; CMOS technology; Capacitance; Circuits; Frequency; MOSFETs; Operational amplifiers; Power amplifiers; Power supplies; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on

Print_ISBN

0-7803-8346-X

Type

conf

DOI

10.1109/MWSCAS.2004.1353919

Filename

1353919