False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

Author

Liou, Jing-Jia ; Krstic, Angela ; Wang, Li.-C. ; Cheng, Kwang-Ting

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA

fYear

2002

fDate

2002

Firstpage

566

Lastpage

569

Abstract

We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths.

Keywords

VLSI; cellular arrays; circuit optimisation; delays; integrated circuit interconnections; integrated circuit modelling; logic CAD; statistical analysis; timing; VLSI; cell delays; circuit delay distribution; correlated random variables; delay testing; efficient path selection; false-path-aware analysis; interconnect delays; statistical timing analysis; timing optimization; timing validation; true critical paths; Algorithm design and analysis; Circuit testing; Delay estimation; Integrated circuit interconnections; Logic; Performance analysis; Permission; Probability; Statistical analysis; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2002. Proceedings. 39th

ISSN

0738-100X

Print_ISBN

1-58113-461-4

Type

conf

DOI

10.1109/DAC.2002.1012689

Filename

1012689

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1851771