Optimized multi-stage minimum-distance-search circuit with feedback-stabilization for fully-parallel associative memories

In this paper, we deal with a fully-parallel associative memory that compares differences between input data and stored reference data, and outputs the most resembling or nearest matching reference data. The multi-stage minimum-distance-search circuit, being the key circuit for this functionality, is optimized for maximum speed at low cost in power dissipation. In particular the first stage of the minimum-distance-circuit, called "winner-line-up amplifier" turned out to have considerable improvement potential through pre-charging of its internal nodes. In consequence, the maximum search time of an associative memory having 128 reference patterns, each containing 496 equivalent bit, could be cut down by about 37% to less than 180 ns for an implementation in 350 nm CMOS. The maximum average-power dissipation increase for realizing this speed-up could be kept as small as 17% remaining below 176 mW.