An RF sampling downconversion filter for a receiver front-end

Author

Jakonis, D. ; Folkesson, K. ; Svensson, C. ; Dabrowski, J. ; Eriksson, P.

Author_Institution

Dept. of Electr. Eng., Linkoping Univ., Sweden

Volume

1

fYear

2004

fDate

25-28 July 2004

Abstract

An integrable front-end architecture for WLAN applications in the 2.4 GHz band is described in this paper. It is based on a multi-functional switched-capacitor block, which performs RF sampling, quadrature downconversion to IF, tunable IF filtering, downconversion to baseband, and sampling rate decimation. The proposed RF sampling downconversion filter is designed in a 0.18-μm CMOS technology. In the downconverted channel band the anti-alias suppression is more than 26 dB. The signal gain is 8 dB, the noise figure is 22 dB, and the IIP₃ is at +11 dBm. The image rejection is better than 66 dB. Without the clock generation block the sampling mixer and downconversion filter consume 2.9 mW power.

Keywords

CMOS analogue integrated circuits; UHF filters; UHF integrated circuits; UHF mixers; integrated circuit design; radio receivers; sample and hold circuits; switched capacitor filters; wireless LAN; 0.18 micron; 2.4 GHz; 2.9 mW; 22 dB; 8 dB; CMOS technology; IF filtering; RF sampling downconversion filter; WLAN; anti-alias suppression; image rejection; integrated circuit design; multifunctional switched capacitor filter; receiver front end architecture; sample and hold circuits; sampling mixer; sampling rate decimation; Baseband; CMOS technology; Filtering; Filters; Gain; Image sampling; Noise figure; Radio frequency; Sampling methods; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on

Print_ISBN

0-7803-8346-X

Type

conf

DOI

10.1109/MWSCAS.2004.1353923

Filename

1353923