DocumentCode
1851854
Title
S-Tree: a technique for buffered routing tree synthesis
Author
Hrkic, Milos ; Lillis, John
Author_Institution
CS Dept., Illinois Univ., Chicago, IL, USA
fYear
2002
fDate
2002
Firstpage
578
Lastpage
583
Abstract
Presents the S-Tree algorithm for synthesis of buffered interconnects. The approach incorporates a unique combination of real-world issues (handling of routing and buffer blockages, cost minimization, critical sink isolation, sink polarities), robustness and scalability. The algorithm is able to achieve the slack comparable to that of buffered P-Tree using less resources (wire and buffers) in an order of magnitude less CPU time.
Keywords
circuit layout CAD; circuit optimisation; integrated circuit interconnections; integrated circuit layout; network routing; timing; trees (mathematics); CPU time; S-Tree; Steiner trees; buffer blockages; buffered interconnects; buffered routing tree synthesis; cost minimization; critical sink isolation; integrated circuit design; robustness; scalability; sink polarities; timing optimization; wire; Costs; Integrated circuit interconnections; Integrated circuit synthesis; Minimization; Permission; Routing; Scalability; Timing; Topology; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2002. Proceedings. 39th
ISSN
0738-100X
Print_ISBN
1-58113-461-4
Type
conf
DOI
10.1109/DAC.2002.1012692
Filename
1012692
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