Title :
An algorithm for integrated pin assignment and buffer planning
Author :
Xiang, Hua ; Tang, Xiaoping ; Wong, D.F.
Author_Institution :
Texas Univ., Austin, TX, USA
Abstract :
The buffer block methodology has become increasingly popular as more and more buffers are needed in deep-submicron design, and it leads to many challenging problems in physical design. In this paper, we present a polynomial-time exact algorithm for integrated pin assignment and buffer planning for all two-pin nets from one macro block (source block) to all other blocks of a given buffer block plan as well as minimizing the total cost α·W+β·R for any positive α and β where W is the total wire length and R is the number of buffers. By applying this algorithm iteratively (each time pick one block as the source block), it provides a polynomial-time algorithm for pin assignment and buffer planning for nets among multiple macro blocks. Experimental results demonstrate its efficiency and effectiveness.
Keywords :
VLSI; buffer circuits; circuit layout CAD; integrated circuit interconnections; integrated circuit layout; network routing; wiring; IC design; VLSI; buffer block methodology; buffer block plan; buffer planning; deep-submicron design; integrated pin assignment; interconnects; multiple macro blocks; physical design; polynomial-time exact algorithm; routing; total wire length; two-pin nets; Algorithm design and analysis; Computer applications; Costs; Integrated circuit interconnections; Iterative algorithms; Permission; Pins; Polynomials; Routing; Wire;
Conference_Titel :
Design Automation Conference, 2002. Proceedings. 39th
Print_ISBN :
1-58113-461-4
DOI :
10.1109/DAC.2002.1012693
