Computationally efficient coherent correlator design for DVB-S2 receiver

Computational complexity of a coherent correlator is dominated by the number of complex multiplications and additions involved in process. In this paper a unique multiplier-less approach of coherent correlation has been proposed for Digital Video Broadcasting Second Generation (DVB-S2) receiver. It can be used in high speed communication of DVB-S2 because of its simplified architecture. The proposed design shows a huge amount of hardware saving as well as it improves the processing speed of the correlator over the conventional approach. It is also advantageous in terms of On-chip memory requirement. The functionality of the design has been verified through simulation and synthesis of the existing and proposed correlation scheme. The proposed architecture is optimized in terms of area with 97% reduction in number of LUTs. The critical speed of design on Virtex4 FPGA is 1364 MHz and it consumes 1.29 W power which is 9.28% of the power consumed by conventional architectures. The proposed coherent correlator architecture can be used with the Data Aided (DA) receiver schemes (such as Frame synchronization, SNR estimation) used in the DVB-S2 standard.