CMOS low noise amplifier design optimization technique

In this paper, a set up noise parameter expression and the third order intermodulation product expression (IM3) for a power-constrained simultaneous noise and input matching low noise amplifier design optimization technique are introduced. Based on these expressions, the methodology to design LNA to archive the power-constrained simultaneous noise and input matching as well as satisfy the linearization condition is explained. In additional, the power gain is enhanced by using a very simple positive feedback. The proposed LNA for 5 GHz WLAN applications is fabricated based on 0.18 μm CMOS technology. Measured results show 20 dB power gain, 1.5 dB NF and -5 dBm IIP3. The proposed LNA dissipates DC current of 3 mA at supply voltage of 2.5 V.