CMOS low noise amplifier design optimization technique

Author

Nguyen, Trung-Kien ; Oh, Nam-Jin ; Choi, Hyung-Chul ; Ihm, Kuk-Ju ; Lee, Sang-Gug

Author_Institution

Inf. & Commun. Univ., Daejeon, South Korea

Volume

1

fYear

2004

fDate

25-28 July 2004

Abstract

In this paper, a set up noise parameter expression and the third order intermodulation product expression (IM3) for a power-constrained simultaneous noise and input matching low noise amplifier design optimization technique are introduced. Based on these expressions, the methodology to design LNA to archive the power-constrained simultaneous noise and input matching as well as satisfy the linearization condition is explained. In additional, the power gain is enhanced by using a very simple positive feedback. The proposed LNA for 5 GHz WLAN applications is fabricated based on 0.18 μm CMOS technology. Measured results show 20 dB power gain, 1.5 dB NF and -5 dBm IIP3. The proposed LNA dissipates DC current of 3 mA at supply voltage of 2.5 V.

Keywords

CMOS integrated circuits; circuit optimisation; feedback; integrated circuit design; integrated circuit noise; intermodulation; linearisation techniques; microwave amplifiers; microwave integrated circuits; wireless LAN; 0.18 micron; 1.5 dB; 2.5 V; 20 dB; 3 mA; 5 GHz; CMOS low noise amplifier design; CMOS technology; WLAN applications; circuit optimization; integrated circuit noise; intermodulation product; linearization; positive feedback; CMOS technology; Design methodology; Design optimization; Feedback; Gain measurement; Impedance matching; Low-noise amplifiers; Noise measurement; Power measurement; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on

Print_ISBN

0-7803-8346-X

Type

conf

DOI

10.1109/MWSCAS.2004.1353928

Filename

1353928