DocumentCode
1852059
Title
A VME 32 ch pipeline TDC module with TMC LSI
Author
Shirasu, Hideki ; Arai, Yasuo ; Ikeno, Masahiro ; Murata, Toshimitsu ; Emura, Tsuneo
Author_Institution
Tokyo Univ. of Agric. & Technol., Japan
Volume
1
fYear
1995
fDate
21-28 Oct 1995
Firstpage
446
Abstract
A new 32-channel pipeline TDC module, which implements custom developed Time Memory Cell LSIs, has been developed for high-rate wire-chamber applications. The module achieved 370 ps time resolution and records data for a period of 3.2 μsec. To handle the large data size, a digital signal processor (DSP56002) is implemented in the module. Most of the control logics are implemented in two complex PLDs to achieve the density of 32 channels in a single-width, double-height VME module
Keywords
detector circuits; nuclear electronics; system buses; 32-channel pipeline TDC module; DSP56002; TMC LSI; Time Memory Cell LSIs; VME 32 ch pipeline TDC module; complex PLDs; control logics; data size; digital signal processor; high-rate wire-chamber applications; single-width double-height VME module; time resolution; CMOS technology; Clocks; Costs; Digital signal processing chips; Digital signal processors; Frequency; Large scale integration; Pipelines; Signal resolution; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Nuclear Science Symposium and Medical Imaging Conference Record, 1995., 1995 IEEE
Conference_Location
San Francisco, CA
Print_ISBN
0-7803-3180-X
Type
conf
DOI
10.1109/NSSMIC.1995.504264
Filename
504264
Link To Document