Realization of a dynamically reconfigurable preprocessor

Our research demonstrates the feasibility of employing field programmable gate arrays (FPGAs) to realize high-speed algorithm-specific processing architectures for avionic signal processing applications. Architectures composed of FPGAs provide a low-cost and flexible alternative to custom hard-wired preprocessors and a lower-cost, physically smaller alternative to massively parallel processors (both SIMD and MIMD machines). Algorithm segments which require processing hundreds of millions of operations per second have been mapped into a single FPGA device. This technology may ultimately fill a range of processing requirements in the areas of radar and communication processing as well as image enhancement applications. The application of configurable logic devices allows realization of processing architectures to efficiently compute low-level algorithmic functions, or segments. Reconfiguration of FPGAs to implement several algorithm segments is analogous to selecting subroutines to form a software algorithm suite in a conventional processor, since it can be accomplished without hardware modification