Title :
Unlocking the design secrets of a 2.29 Gb/s Rijndael processor
Author :
Schaumont, Patrick R. ; Kuo, Henry ; Verbauwhede, I.M.
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 Gb/s of encryption throughput at 56 mW of power consumption. We discuss how the high level reference specification in C is translated into a parallel architecture. Design decisions are motivated from a system level viewpoint. The prototyping setup is discussed.
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; cryptography; high level synthesis; high-speed integrated circuits; integrated circuit design; parallel architectures; pipeline processing; 0.18 micron; 1.8 V; 2.29 Gbit/s; 56 mW; Advanced Encryption Standard compliant encryption chip; C specification; CMOS technology; HDL design; Rijndael processor; design; design decisions; encryption speed; high level reference specification; high-speed hardware accelerator; parallel architecture; performance testing; pipelining; power consumption; power-optimized domain specific processors; prototyping setup; system level viewpoint; CMOS technology; Cryptography; Energy consumption; Instruments; Parallel architectures; Permission; Power system security; Prototypes; Testing; Throughput;
Conference_Titel :
Design Automation Conference, 2002. Proceedings. 39th
Print_ISBN :
1-58113-461-4
DOI :
10.1109/DAC.2002.1012702
