Synthesis of CMOS multiplier structures using multifunctional circuits

The paper will present new high accuracy multiplier circuits, focused on the implementation of original techniques for improving the linearity of the proposed structures. The new approach of designing high precision multipliers using multifunctional cores presents the important advantage of allowing a facile reconfiguration of the designed circuits, the multiplier core being able to implement a multitude of additional circuit functions: amplifying, squaring and square-rooting or simulating a positive and negative equivalent resistance. The multiplier structures are designed for low-voltage low-power operation (the supply voltage is ±1.8V for implementing in 0.18μm CMOS technology and the current consumption is smaller than 50/μA for any proposed multiplier).