Title :
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Author :
Chandra, Anshuman ; Chakrabarty, Krishnendu
Author_Institution :
Dept. Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
Abstract :
We present a test resource partitioning (TRP) technique that simultaneously reduces test data volume, test application time and scan power The proposed approach is based on the use of alternating run-length codes for test data compression. Experimental results for the larger ISCAS-89 benchmarks and an IBM production circuit show that reduced test data volume, test application time and low power scan testing can indeed be achieved in all cases.
Keywords :
automatic test equipment; automatic test pattern generation; boundary scan testing; data compression; integrated circuit testing; low-power electronics; runlength codes; system-on-chip; ATE; ATPG techniques; FDR codes; IBM production circuit; ISCAS-89 benchmarks; SOC; alternating run-length codes; low power scan testing; scan power reduction; test application time reduction; test data compression; test data volume reduction; test resource partitioning technique; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit testing; Energy consumption; Integrated circuit reliability; Power system reliability; System testing; System-on-a-chip; Test data compression;
Conference_Titel :
Design Automation Conference, 2002. Proceedings. 39th
Print_ISBN :
1-58113-461-4
DOI :
10.1109/DAC.2002.1012710
