DocumentCode
1852466
Title
Embedded test control schemes for compression in SOCs
Author
Kay, Douglas ; Chung, Sung ; Mourad, Samiha
Author_Institution
Cisco Syst., San Jose, CA, USA
fYear
2002
fDate
2002
Firstpage
679
Lastpage
684
Abstract
This paper presents novel control schemes for testing embedded cores in a system on a chip (SOC). It converts a traditional BIST scheme into an externally controllable scheme to achieve a high test quality within optimal test execution time without inserting test points. The scheme promotes design and test reuse without revealing IP information.
Keywords
built-in self test; data compression; embedded systems; integrated circuit testing; resource allocation; system-on-chip; BIST scheme; SOCs; compression; control schemes; data compression; embedded core testing; embedded test control schemes; externally controllable scheme; high test quality; optimal test execution time; system on chip; test resource allocation; Bandwidth; Built-in self-test; Circuit faults; Circuit testing; Costs; Fault detection; Permission; System testing; System-on-a-chip; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2002. Proceedings. 39th
ISSN
0738-100X
Print_ISBN
1-58113-461-4
Type
conf
DOI
10.1109/DAC.2002.1012711
Filename
1012711
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