Title :
Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs
Author :
Iyengar, Varun ; Chakrabarty, Krishnendu ; Marinissen, Erik Jan
Author_Institution :
Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
Abstract :
This paper describes an integrated framework for plug-and-play SOC test automation. This framework is based on a new approach for wrapper/TAM co-optimization based on rectangle packing. We first tailor TAM widths to each core´s test data needs. We then use rectangle packing to develop an integrated scheduling algorithm that incorporates precedence and power constraints in the test schedule, while allowing the SOC integrator to designate a group of tests as preemptable. Finally, we study the relationship between TAM width and tester data volume to identify an effective TAM width for the SOC. We present experimental results for non-preemptive, preemptive, and power-constrained test scheduling, as well as for effective TAM width identification for an academic benchmark SOC and three industrial SOCs.
Keywords :
automatic testing; circuit optimisation; integrated circuit testing; processor scheduling; system-on-chip; SOC; TAM width; benchmark SOC; constraint-driven test scheduling; industrial SOCs; integrated framework; integrated scheduling algorithm; nonpreemptive test scheduling; plug-and-play test automation; power constraints; power-constrained test scheduling; precedence constraints; preemptive test scheduling; rectangle packing; test access mechanisms; tester data volume reduction; wrapper/TAM co-optimization; Automatic testing; Circuit testing; Costs; Design automation; Integrated circuit testing; Job shop scheduling; Logic testing; Pins; Processor scheduling; System testing;
Conference_Titel :
Design Automation Conference, 2002. Proceedings. 39th
Print_ISBN :
1-58113-461-4
DOI :
10.1109/DAC.2002.1012712