Title :
32-bit PI-bus versus 32-bit Futurebus+ performance comparison
Abstract :
This paper presents a performance analysis of the JIAWG 32-bit Parallel Intermodule (PI) Bus versus a 32-bit Futurebus+ Standard backplane bus. Performance was measured in terms of bus throughput and latency, using a test scenario representative of a real-time, avionics application. The test scenario communications mix was constructed using Rate Monotonic Scheduling (RMS) theory. Behavioral VHDL models of both buses were used to execute the test scenario in a VHDL simulation environment. Simulation results were used to test whether critical deadlines were met for a given bus utilization (throughput) level. PI-Bus performance using the datagram, short-header, non-acknowledged format was compared to Futurebus+ performance using compelled mode, both with and without the message-passing protocol defined in IEEE Futurebus+ 896.1
Keywords :
aerospace computing; aircraft instrumentation; data communication equipment; digital simulation; message passing; performance evaluation; peripheral interfaces; specification languages; system buses; 32 bit; 32-bit Futurebus+ Standard backplane bus; IEEE Futurebus+ 896.1; JIAWG 32-bit Parallel Intermodule Bus; PI-bus; Rate Monotonic Scheduling theory; VHDL simulation environment; avionics; behavioral VHDL models; bus throughput; compelled mode; critical deadlines; datagram; latency; message-passing protocol; performance analysis; real-time; short-header; test communications mix; Aerospace electronics; Analytical models; Backplanes; Delay; Performance analysis; Processor scheduling; Protocols; Stress; System testing; Throughput;
Conference_Titel :
Aerospace and Electronics Conference, 1993. NAECON 1993., Proceedings of the IEEE 1993 National
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-1295-3
DOI :
10.1109/NAECON.1993.290909
