An efficient implementation of CBC mode Rijndeal AES on an FPGA

Due to the exponential growth of wireless and mobile applications, security has become a paramount design aspect. In this paper we propose an area optimized design for the Rijndeal advanced encryption standard (AES), in the cipher block chaining (CBC) mode. The design is performed using mentor graphics FPGA Adv.Pro. The implementation is performed on XILINX Vertex2P, XC2VP30-7ff896 and utilizes 13% of its resources. The maximum frequency is 405.227 MHz, the output of encryption/decryption takes 60 clock cycles for processing one block message.