Design of the HERA-B first level trigger

The HERA-B first level trigger (FLT) mainly identifies lepton pairs from J/ψ decays. It reduces a 10 MHz input rate by a factor of 200 with a mean latency of ≈5 μs. The FLT is a hardware processor consisting of track finding units (TFUs), track parameter units (TPUs), and a trigger decision unit (TDU). Tracking chamber data are transferred at a rate of ≈600 Gbit/s into memories distributed over the TFUs. 12 serial link chips, each providing a bandwidth of 1.8 Gbit/s, will be used per TFU. Between 4 and 14 TFUs are assigned to different sections of each layer of tracking chambers so that their load is balanced. In total 60 TFUs are used to equip the 7 tracking layers. For the current bunch crossing, a coincidence matrix identifies track hits in the search region using 3 stereo views of the assigned tracking chamber section. The improved search region, extrapolated to the next tracking chamber superlayer, is read from a lookup table and transmitted to one or more TFUs assigned to the next superlayer. If the track is followed through all tracking chambers the last TFU communicates the track parameters to a TPU. The TPU determines from the transmitted track information the kinematic parameters of the lepton candidate to accept or reject it. Finally the tracks of the same event are collected in the TDU. It computes the invariant mass of track pairs to make the final trigger decision. The system is in the board layout stage. Prototype testing is scheduled for begin of 1996