FPGA implementation of RDR Manchester and D-Manchester CODEC design for Wireless Transceiver

This paper presents a VLSI hardware implementation of a manchester and differential manchester coder / decoder systems. VHDL (VHSIC hardware description language) has been used for describing the hardware of the circuit, and field programmable gate arrays (FPGAs) has been used for the hardware implementation task. The data rate can be easily reconfigured, since the target technology (FPGA) can be reprogrammed unlimited number of times. The manchester / differential manchester codec can be used for the serial data transmission and reception of the ER400TRS wireless transceiver system.