FPGA implementation of RDR Manchester and D-Manchester CODEC design for Wireless Transceiver

Author

Medany, Wael M El

Author_Institution

Dept. of Commun. & Electr. Eng., Fayoum Univ., Faiyum

fYear

2008

fDate

18-20 March 2008

Firstpage

1

Lastpage

5

Abstract

This paper presents a VLSI hardware implementation of a manchester and differential manchester coder / decoder systems. VHDL (VHSIC hardware description language) has been used for describing the hardware of the circuit, and field programmable gate arrays (FPGAs) has been used for the hardware implementation task. The data rate can be easily reconfigured, since the target technology (FPGA) can be reprogrammed unlimited number of times. The manchester / differential manchester codec can be used for the serial data transmission and reception of the ER400TRS wireless transceiver system.

Keywords

VLSI; codecs; field programmable gate arrays; hardware description languages; telecommunication computing; transceivers; D-manchester codec design; FPGA implementation; VLSI hardware implementation; differential manchester coder decoder systems; field programmable gate arrays; hardware description language; manchester differential manchester codec; serial data transmission; wireless transceiver system; Bit rate; Codecs; Communication standards; Decoding; Design engineering; Field programmable gate arrays; Frequency shift keying; Hardware; Transceivers; Very large scale integration; FPGA; Manchester Code; VHDL; VLSI; Wireless;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Science Conference, 2008. NRSC 2008. National

Conference_Location

Tanta

Print_ISBN

978-977-5031-95-2

Type

conf

DOI

10.1109/NRSC.2008.4542375

Filename

4542375