A 5mW 19–43 GHz broadband CMOS I/Q frequency divider

Author

Sharaf, Khaled M.

Author_Institution

Integrated Circuits Lab., Ain-Shams Univ., Cairo

fYear

2008

fDate

18-20 March 2008

Firstpage

1

Lastpage

8

Abstract

A comparison of three designs of high-frequency broadband frequency dividers is presented. The designs are optimized for high operating frequencies. Two recently published dynamic-loading frequency divider designs are optimized for their highest attainable speed. The third proposed frequency divider features a modified dynamic-loading master-slave D-latches with on-chip spiral inductors at its differential clock inputs. The proposed frequency divider is designed in TSMC 0.13-mum CMOS process and can operate in the 19-43 GHz range and dissipates 5 mW from a supply voltage of 1.5 V.

Keywords

CMOS analogue integrated circuits; MIMIC; MMIC; frequency dividers; integrated circuit design; low-power electronics; TSMC; broadband CMOS I/Q frequency divider; differential clock inputs; dynamic-loading frequency divider design; dynamic-loading master-slave D-latches; frequency 19 GHz to 43 GHz; on-chip spiral inductors; power 5 mW; size 0.13 mum; voltage 1.5 V; CMOS process; Clocks; Design engineering; Design optimization; Frequency conversion; Master-slave; Radiofrequency integrated circuits; Signal generators; Topology; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Science Conference, 2008. NRSC 2008. National

Conference_Location

Tanta

Print_ISBN

978-977-5031-95-2

Type

conf

DOI

10.1109/NRSC.2008.4542379

Filename

4542379